Publications

Neuromorphic Intermediate Representation for FPGA Prototype

Faras Siddiqui, Ayesh Ahmad

Manuscript in preparation; internal review phase (2025)

This work presents a clean-room intermediate representation designed for deploying spiking neural networks to custom neuromorphic FPGA hardware. The IR addresses limitations in existing frameworks by providing a minimal, type-safe schema optimized for hardware synthesis.

Key contributions include a novel scalar parameter optimization technique achieving 1024x memory reduction, full round-trip serialization via HDF5, and production validation on event-based vision benchmarks.